1. Field of the Invention
The present invention relates generally to a semiconductor chip test system, and more particularly, to a system and method for increasing a number of semiconductor chips to be tested in parallel.
2. Description of Related Art
A conventional semiconductor chip test system includes a tester, a probe card, and semiconductor chips to be tested.
The conventional semiconductor chip test system is limited by the number of the semiconductor chips capable of being tested in parallel. For example, if there are 64 input/output pins on the tester of the semiconductor chip test system, the test system can test only 8 semiconductor chips in parallel each of which have eight (8) input/output pins.
FIG. 1 shows a schematic block diagram of the conventional semiconductor chip test system including the tester 10, semiconductor chips 12-1˜12-n, and a probe card 14.
Symbols I/O11˜1k, I/O21˜2k, . . . , I/On1˜nk are indicative of data input/output lines connected between data input/output pads (or, pins) of the semiconductor chips 12-1˜12-n and data input/output pins (not shown) of the tester 10. Symbols ADD and COM are indicative of address and command input lines connected between address and command input pins (not shown) of the tester 10 and address and command input pads (or pins) (not shown) of the semiconductor chips 12-1˜12-n. A symbol POWER is indicative of power supplying lines connected between power supply pins (not shown) of the tester 10 and power supplying pads (or pins) of the semiconductor chips 12-1˜12-n.
The tester 10 inputs/outputs data from/to the semiconductor chips 12-1˜12-n comprising k data input/output pads (or pins) through the data input/output lines I/O11˜1k . . . I/On1˜nk, outputs the address and the command to the semiconductor chips 12-1˜12-n through the address and command output lines ADD and COM, and applies the power supply through the power supplying lines POWER. At this time, the data are transferred between the tester 10 and the semiconductor chips 12-1˜12-n through the probe card 14. Also, the address, the command, and the power supply are applied from the tester 10 to the semiconductor chips 12-1˜12-n through the probe card 14. When the semiconductor chips are tested at a wafer level, the tester 10 is connected to the data input/output pads of the chips. When the semiconductor chips are tested at a package level, the tester 10 is connected to the data input/output pins of the chips.
In the test system described above, there is no problem in that the address and the command output lines ADD and COM, and the power supplying lines POWER are commonly connected from the tester 10 to the n semiconductor chips 12-1˜12-n. In other words, the tester 10 outputs a signal through the address and command output lines ADD and COM, and the power supplying lines POWER. The signal lines are configured to be in n groups and being connected to each of n semiconductor chips 12-1˜12-n through the probe card 14.
However, n groups of the data input/output lines ((I/O11˜I/O1k)˜(I/On1˜I/Onk)) of the tester 10 are not commonly connected to n semiconductor chips 12-1˜12-n but are connected to each of n semiconductor chips 12-1˜12-n, since data which is written from the tester to the semiconductor chips is same, but data which is read from the semiconductor chips to the tester can be different.
Accordingly, the conventional semiconductor chip test system can not commonly use the data input/output lines, and thus, if the number of the data input/output pads (or pins) of each of n semiconductors chips 12-1˜12-n is k, the conventional semiconductor test system has to input/output the data through nk data input/output lines. As a result, the number of the semiconductor chips to be tested are limited to the number of the data input/output pins of the tester of the semiconductor chip test system.